The interest in nonvolatile resistive oxide-based memories is grounded in the fact that such memories can offer outstanding switching performances, including faster switching speed, lower energy consumption per bit, lower manufacturing cost, and higher endurance, as well as the potential for scalability to high-density when compared to traditional Si-based memories. By exploiting oxide-based materials, a variety of integrated architectures for a high-density array have been suggested, such as one-diode-one-resistor (1D-1R), one-selector-one-resistor (1S-1R), complementary resistive switch (CRS), and three-dimensional (3D) cross-point arrays. In fact, the integration of these architectures is important for a crossbar array in order to eliminate undesirable misreading of the switching states. This occurs on the selected cell by parasitic sneak current through unselected cells, which is called crosstalk. Many architectures show the crosstalk problems at a crossbar array over 1 Mbit in density. For example, when the number of word/bit lines in the crossbar array is increased, the sneak current through the unselected cells and its paths are simultaneously increased, and they can then interrupt the reading process at a selected cell at a certain number of arrays. Under these circumstances, the maximum size of the array is strictly limited. Furthermore, the fabrication of the suggested architectures often requires many prerequisite high temperature processing steps such as deposition or annealing, which could lead to high cost and low device yields. Another important consideration is that the operating I-V of the diode or selector device must be matched to the operating range of the memory device, which can limit the number of materials available.
Recently, as an effort to mitigate these issues, diverse selector-less resistive memories that show a self-embedded nonlinear I-V characteristic have been suggested and investigated. However, they still suffer from inefficient non-linearity values that limit the maximum number of word/bit lines in the integrated array. In addition, many of these resistive memories require multiple oxide layers. If the stoichiometry of the active materials is not tightly controlled there could be switching non-uniformity.
In order to resolve the aforementioned issues and limitations, current strategies for making memory devices with a crossbar structure need to be improved and modified.